Computer Architecture

CPU & Microprocessors

• The **CPU** (Central Processing Unit) is the brain of the computer; its purpose is to **fetch**, **decode**, and **execute** instructions.
• A **microprocessor** is a single-chip integrated circuit that contains the CPU and may also include memory controllers and I/O interfaces.
• The CPU processes data by taking input, executing instructions, and producing output.

Von Neumann Architecture

• Proposed by John Von Neumann in the 1940s; most general-purpose computers are based on this design.
• Key components: **Control Unit (CU)**, **Arithmetic Logic Unit (ALU)**, and **registers**.
• **ALU** performs arithmetic operations (e.g., ADD) and logical decisions (e.g., IF X > 5).
• **CU** coordinates data movement and decodes instructions fetched from memory.
• Registers are extremely small, fast memory inside the CPU; each has a specific purpose.
• Five main registers: **PC**, **MAR**, **MDR**, **CIR**, **ACC**.
• **PC** (Program Counter) holds the address of the next instruction to be executed; increments by 1 each cycle.
• **MAR** (Memory Address Register) holds the address of data/instruction to be fetched from memory.
• **MDR** (Memory Data Register) stores data/instruction fetched from memory.
• **CIR** (Current Instruction Register) stores the instruction currently being decoded/executed.
• **ACC** (Accumulator) stores results of calculations from the ALU.

Buses

• A **bus** is a set of parallel wires connecting components; transmits data/signals.
• **Address bus** – unidirectional; carries memory addresses (locations).
• **Data bus** – bidirectional; carries data or instructions.
• **Control bus** – bidirectional; carries commands/control signals (e.g., read/write).

Fetch-Decode-Execute Cycle

• The CPU repeats the **fetch-decode-execute** cycle billions of times per second.
• **Fetch**: PC address → MAR → address bus → memory → data bus → MDR → CIR; PC increments.
• **Decode**: CU splits instruction into **opcode** (what to do) and **operand** (data/address).
• **Execute**: CPU carries out the instruction (e.g., calculation, store result, fetch new data).
• The cycle then repeats with the next instruction.

Characteristics of the CPU

• **Clock speed** – measured in Hz (GHz); number of FDE cycles per second. Higher speed = more instructions per second.
• **Cache size** – small, fast memory on/near CPU; stores frequently used instructions/data. Larger cache reduces fetches from RAM, improving speed.
• **Number of cores** – each core is an independent processing unit. Multi-core CPUs can execute multiple instructions simultaneously (parallel processing).
• Example: Quad-core at 3 GHz can process up to 12 billion instructions per second.

CPU Instruction Sets

• An **instruction set** is the list of all commands a CPU can execute; each command has a binary **machine code**.
• Instructions have a **mnemonic** (e.g., ADD, SUB, LDA, STA, HLT) and a binary code.
• After decoding, the CPU matches the instruction to its set to know the operation.
• Instruction sets are **machine-specific**; a program for one CPU (e.g., Intel) won't run on another (e.g., ARM).

Embedded Systems

• An **embedded system** is a computer system dedicated to a single function inside a larger mechanical unit.
• Examples: washing machines, car engine management systems, traffic lights, heating thermostats.
• Properties: small size, low power consumption, low cost.
• They are not general-purpose computers; they have a microprocessor and perform a specific task.

Von Neumann architecture showing CPU, memory, input/output, and buses.

Fetch stage of the FDE cycle: address flows from PC to MAR to memory; instruction returns via data bus to MDR and CIR.

CPU characteristics: clock speed, cache size, and number of cores affect performance.