Computer Architecture

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CPU & Microprocessors

The CPU (Central Processing Unit) is the brain of the computer; its purpose is to fetch, decode, and execute instructions.
A microprocessor is a single-chip integrated circuit that contains the CPU and may also include memory controllers and I/O interfaces.
The CPU processes data by taking input, executing instructions, and producing output.

Von Neumann Architecture

Proposed by John Von Neumann in the 1940s; most general-purpose computers are based on this design.
Key components: Control Unit (CU), Arithmetic Logic Unit (ALU), and registers.
ALU performs arithmetic operations (e.g., ADD) and logical decisions (e.g., IF X > 5).
CU coordinates data movement and decodes instructions fetched from memory.
Registers are extremely small, fast memory inside the CPU; each has a specific purpose.
Five main registers: PC, MAR, MDR, CIR, ACC.
PC (Program Counter) holds the address of the next instruction to be executed; increments by 1 each cycle.
MAR (Memory Address Register) holds the address of data/instruction to be fetched from memory.
MDR (Memory Data Register) stores data/instruction fetched from memory.
CIR (Current Instruction Register) stores the instruction currently being decoded/executed.
ACC (Accumulator) stores results of calculations from the ALU.

Buses

A bus is a set of parallel wires connecting components; transmits data/signals.
Address bus – unidirectional; carries memory addresses (locations).
Data bus – bidirectional; carries data or instructions.
Control bus – bidirectional; carries commands/control signals (e.g., read/write).

Fetch-Decode-Execute Cycle

The CPU repeats the fetch-decode-execute cycle billions of times per second.
Fetch: PC address → MAR → address bus → memory → data bus → MDR → CIR; PC increments.
Decode: CU splits instruction into opcode (what to do) and operand (data/address).
Execute: CPU carries out the instruction (e.g., calculation, store result, fetch new data).
The cycle then repeats with the next instruction.

Characteristics of the CPU

Clock speed – measured in Hz (GHz); number of FDE cycles per second. Higher speed = more instructions per second.
Cache size – small, fast memory on/near CPU; stores frequently used instructions/data. Larger cache reduces fetches from RAM, improving speed.
Number of cores – each core is an independent processing unit. Multi-core CPUs can execute multiple instructions simultaneously (parallel processing).
Example: Quad-core at 3 GHz can process up to 12 billion instructions per second.

CPU Instruction Sets

An instruction set is the list of all commands a CPU can execute; each command has a binary machine code.
Instructions have a mnemonic (e.g., ADD, SUB, LDA, STA, HLT) and a binary code.
After decoding, the CPU matches the instruction to its set to know the operation.
Instruction sets are machine-specific; a program for one CPU (e.g., Intel) won't run on another (e.g., ARM).

Embedded Systems

An embedded system is a computer system dedicated to a single function inside a larger mechanical unit.
Examples: washing machines, car engine management systems, traffic lights, heating thermostats.
Properties: small size, low power consumption, low cost.
They are not general-purpose computers; they have a microprocessor and perform a specific task.

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1.What is the purpose of the Central Processing Unit (CPU)?
Easy
- ATo fetch, decode and execute instructions
- BTo store data permanently
- CTo manage input and output devices only
- DTo provide a user interface
2.Which component of the Von Neumann architecture performs arithmetic operations and logical decisions?
Easy
- AControl Unit (CU)
- BArithmetic Logic Unit (ALU)
- CMemory Address Register (MAR)
- DAccumulator (ACC)
3.During the fetch stage of the fetch-decode-execute cycle, what happens to the Program Counter (PC)?
Easy
- AIt is decremented by 1
- BIt is incremented by 1
- CIt is reset to zero
- DIt remains unchanged
4.Which register holds the memory address of the next instruction to be fetched?
Easy
- AMemory Address Register (MAR)
- BProgram Counter (PC)
- CMemory Data Register (MDR)
- DCurrent Instruction Register (CIR)
5.Which bus is unidirectional and carries only memory addresses?
Easy
- AData bus
- BControl bus
- CAddress bus
- DSystem bus
6.What is the role of the control unit during the fetch stage?
Medium
- AIt sends a signal on the control bus to start a read operation
- BIt places the instruction on the data bus
- CIt increments the Program Counter
- DIt stores the fetched instruction in the CIR
7.A computer has a quad-core processor running at 3 GHz. How many instructions can it theoretically execute per second?
Medium
- A3 billion
- B12 billion
- C4 billion
- D7 billion
8.Which of the following is an example of an embedded system?
Easy
- ALaptop
- BDesktop computer
- CWashing machine
- DSmartphone

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9.In the instruction set table, what does the mnemonic 'LDA' stand for?
Easy
- ALoad the value stored in a memory location into the accumulator
- BStore the value in the accumulator in memory
- CAdd a value to the accumulator
- DSubtract a value from the accumulator
10.What is the difference between a CPU and a microprocessor?
Medium
- AA microprocessor is a chip that may include the CPU and other components; the CPU is a component within it
- BA CPU is a chip that may include the microprocessor; the microprocessor is a component within it
- CThey are the same thing
- DA microprocessor is slower than a CPU
11.Which of the following is NOT a characteristic that affects CPU performance?
Easy
- AClock speed
- BCache size
- CNumber of cores
- DRAM size
12.What does the Accumulator (ACC) store?
Easy
- AThe memory address of the next instruction
- BThe results of calculations performed by the ALU
- CThe instruction currently being decoded
- DThe data fetched from memory
13.A computer has a quad-core processor running at 2.5 GHz. What is the maximum number of instructions it can theoretically execute per second?
Medium
- A2.5 billion
- B10 billion
- C2.5 million
- D10 million
14.In the fetch-decode-execute cycle, what is the first action that occurs when the CPU begins to fetch an instruction?
Medium
- AThe instruction is copied from the MDR to the CIR
- BThe address in the PC is copied to the MAR
- CThe control unit sends a read signal on the control bus
- DThe data bus carries the instruction to the MDR
15.In the Von Neumann architecture, which component performs arithmetic operations and logical comparisons?
Easy
- AControl Unit (CU)
- BArithmetic Logic Unit (ALU)
- CAccumulator (ACC)
- DMemory Data Register (MDR)
16.A computer with a single-core 3 GHz processor has 2 MB of cache. A second computer has a dual-core 2 GHz processor with 4 MB of cache. Which statement about performance is correct?
Hard
- AThe single-core computer will always be faster because it has a higher clock speed
- BThe dual-core computer will always be faster because it has more cores and more cache
- CThe dual-core computer may perform better for multi-tasking, but the single-core may be faster for single-threaded tasks
- DClock speed is the only factor that determines performance
17.Using the instruction set below, what is the result in the accumulator after executing the following instructions in sequence? LDA #10 ADD #5 SUB #3
Medium
- A12
- B15
- C8
- D18
18.Which of the following best describes the role of the Current Instruction Register (CIR)?
Easy
- AIt holds the address of the next instruction to be fetched
- BIt stores the result of calculations performed by the ALU
- CIt holds the instruction currently being decoded or executed
- DIt stores data fetched from memory before it is used
19.During the fetch stage, what happens to the Program Counter (PC)?
Easy
- AIt is set to zero
- BIt is incremented by 1
- CIt is copied to the Accumulator
- DIt is decremented by 1
20.A program written for an Intel processor will not run on an ARM processor. What is the most likely reason?
Easy
- AThe clock speeds are different
- BThe cache sizes are different
- CThe instruction sets are different
- DThe number of cores is different
21.Which register holds the memory address of where data or instructions are to be fetched from?
Easy
- AProgram Counter (PC)
- BMemory Address Register (MAR)
- CMemory Data Register (MDR)
- DCurrent Instruction Register (CIR)
22.A student measures the clock speed of two processors. Processor A has a clock speed of 2.4 GHz. Processor B has a clock speed of 1.8 GHz. Which statement about the processors is correct?
Medium
- AProcessor A can execute more instructions per second than Processor B.
- BProcessor B can execute more instructions per second than Processor A.
- CBoth processors execute the same number of instructions per second.
- DThe clock speed does not affect the number of instructions executed per second.
23.A computer has a quad-core processor running at 3 GHz. Each core can execute one instruction per clock cycle. What is the maximum number of instructions the computer can execute per second?
Medium
- A3 billion
- B12 billion
- C1.5 billion
- D4 billion
24.Which type of bus is used to carry the memory address from the CPU to the memory?
Easy
- AData bus
- BControl bus
- CAddress bus
- DSystem bus
25.During the fetch stage of the fetch-decode-execute cycle, what is the role of the Program Counter (PC)?
Easy
- AIt holds the data that has been fetched from memory.
- BIt holds the address of the next instruction to be fetched.
- CIt stores the result of the current calculation.
- DIt decodes the instruction.
26.A program is written using the instruction set of Processor X. Will it run on a computer with Processor Y, which has a different instruction set?
Easy
- AYes, because all processors understand the same machine code.
- BNo, because each processor has its own unique instruction set.
- CYes, if the program is compiled again for Processor Y.
- DNo, because Processor Y has a different clock speed.
27.Which component of the CPU is responsible for decoding instructions?
Easy
- AArithmetic Logic Unit (ALU)
- BControl Unit (CU)
- CAccumulator (ACC)
- DMemory Data Register (MDR)
28.A computer has 2 MB of cache memory. Another computer has 4 MB of cache memory. All other specifications are identical. Which statement is correct?
Medium
- AThe computer with 2 MB cache will perform better because cache is slower.
- BThe computer with 4 MB cache will perform better because more frequently used data can be stored closer to the CPU.
- CCache size does not affect performance.
- DThe computer with 2 MB cache will perform better because it has less cache to manage.
29.What does the acronym ALU stand for?
Easy
- AArithmetic Logic Unit
- BAdvanced Logic Unit
- CArithmetic Load Unit
- DAlgorithmic Logic Unit
30.During the execute stage of the fetch-decode-execute cycle, which register stores the result of a calculation?
Easy
- AProgram Counter (PC)
- BMemory Address Register (MAR)
- CAccumulator (ACC)
- DCurrent Instruction Register (CIR)
31.A student claims that increasing the number of cores always doubles the performance of a computer. Which statement is correct?
Medium
- AThe student is correct because more cores always mean faster processing.
- BThe student is incorrect because performance depends on software being able to use multiple cores effectively.
- CThe student is correct because each core runs at the same clock speed.
- DThe student is incorrect because more cores reduce the clock speed.
32.Which of the following best describes the purpose of the CPU?
Easy
- ATo store data permanently
- BTo fetch, decode, and execute instructions
- CTo provide a user interface
- DTo connect to the internet
33.What is the purpose of the Control Unit (CU) in the Von Neumann architecture?
Easy
- ATo perform arithmetic and logical operations
- BTo decode instructions and coordinate data movement
- CTo store the results of calculations
- DTo hold the memory address of the next instruction
34.Which register stores the instruction that the CPU is currently decoding or executing?
Easy
- AProgram Counter (PC)
- BMemory Data Register (MDR)
- CCurrent Instruction Register (CIR)
- DAccumulator (ACC)
35.What is the role of the Memory Address Register (MAR)?
Easy
- AIt holds the memory address of where data or instructions are to be fetched from
- BIt stores the data or instruction fetched from memory
- CIt holds the address of the next instruction to be executed
- DIt stores the results of calculations performed by the ALU
36.A computer has a dual-core processor running at 2 GHz. Each core can execute one instruction per clock cycle. What is the maximum number of instructions the computer can theoretically execute per second?
Medium
- A2 billion
- B4 billion
- C2 million
- D4 million
37.Which of the following best describes cache memory?
Easy
- ALarge, slow memory used for long-term storage
- BVery small, very fast memory on or close to the CPU used for temporary storage of frequently used instructions and data
- CMemory that stores the operating system permanently
- DA type of read-only memory that cannot be changed
38.Using the instruction set below, what operation would be performed if the instruction binary code is 10111111? Instruction table: ADD = 10100001 SUB = 00100010 LDA = 10111111 STA = 01100000 HLT = 00000000
Medium
- AADD
- BSUB
- CLDA
- DSTA
39.What does the mnemonic 'STA' typically stand for in an instruction set?
Easy
- AStart
- BStore the value in the accumulator in a specific memory location
- CSubtract and add
- DStop the program
40.A computer has a quad-core processor running at 2.5 GHz. Each core can execute one instruction per clock cycle. What is the maximum number of instructions the computer can execute per second?
Medium
- A2.5 billion
- B5 billion
- C10 billion
- D20 billion
41.Which of the following best describes the purpose of the Central Processing Unit (CPU)?
Easy
- ATo fetch, decode and execute instructions
- BTo store data permanently
- CTo manage input and output devices only
- DTo provide power to the computer
42.A microprocessor is a type of integrated circuit that contains only the CPU and no other components.
Medium
True or false?
43.Which register holds the memory address of the next instruction to be executed?
Easy
- AProgram Counter (PC)
- BMemory Address Register (MAR)
- CMemory Data Register (MDR)
- DCurrent Instruction Register (CIR)
44.The address bus is bidirectional, meaning it can carry data in both directions.
Easy
True or false?
45.A computer has a quad-core processor running at 2 GHz. Each core can execute one instruction per clock cycle. What is the maximum number of instructions the computer can execute per second?
Medium
- A2 billion
- B4 billion
- C8 billion
- D16 billion
46.Which of the following are examples of embedded systems? (Select all that apply)
Medium
- AWashing machine
- BLaptop
- CTraffic light controller
- DDesktop computer
- ESatellite navigation system
47.Arrange the following steps of the fetch-decode-execute cycle in the correct order.
Medium
- The instruction is decoded by the Control Unit.
- The Program Counter is incremented.
- The instruction is fetched from memory into the MDR.
- The instruction is executed by the CPU.
48.Match each CPU register with its correct purpose.
Medium
- Program Counter (PC)
- Memory Address Register (MAR)
- Accumulator (ACC)
- Current Instruction Register (CIR)
- Holds the address of the next instruction to be executed
- Holds the address of data or instructions to be fetched from memory
- Stores the results of calculations performed by the ALU
- Stores the instruction currently being decoded or executed
49.A washing machine contains an embedded system. Which of the following best describes why it is classified as an embedded system?
Medium
- AIt has a general-purpose CPU that can run any software.
- BIt performs a dedicated function inside a larger mechanical unit.
- CIt uses more power than a general-purpose computer.
- DIt has a large amount of RAM for multitasking.
50.During the fetch stage of the fetch-decode-execute cycle, which register is used to temporarily hold the instruction that has just been fetched from memory before it is decoded?
Easy
- AMemory Address Register (MAR)
- BMemory Data Register (MDR)
- CCurrent Instruction Register (CIR)
- DAccumulator (ACC)
51.Complete the sentence.
Easy
The Von Neumann architecture consists of the Control Unit, the Arithmetic Logic Unit, and ____.
52.Fill in the blank.
Easy
During the fetch stage, the address of the next instruction is copied from the Program Counter to the ____.
53.What does the mnemonic 'LDA' stand for in an instruction set?
Easy
54.A single-core processor has a clock speed of 3.2 GHz. Assuming it executes one instruction per clock cycle, calculate the number of instructions it can execute in 1 second. Give your answer in billions.
Easy
55.A quad-core processor has a clock speed of 2.5 GHz. Assuming each core can execute one instruction per clock cycle, what is the maximum number of instructions the processor can execute per second? Give your answer in billions of instructions per second.
Medium
56.A dual-core processor has a clock speed of 2.5 GHz. Assuming each core can execute one instruction per clock cycle, calculate the maximum number of instructions the processor can execute per second. Give your answer in billions of instructions per second.
Medium
57.A computer has a quad-core processor with a clock speed of 2.8 GHz. Assuming each core can execute one instruction per clock cycle, calculate the maximum number of instructions the computer can execute per second. Give your answer in billions.
Medium
58.Complete the following sentence about the fetch-decode-execute cycle.
Medium
During the fetch stage, the address in the ____ is copied to the ____, which then places the address on the ____ bus.
59.What does the mnemonic 'HLT' stand for in an instruction set?
Easy
60.A single-core processor has a clock speed of 3.2 GHz. If it can execute 2 instructions per clock cycle, how many instructions can it execute per second? Give your answer in billions.
Medium
61.A quad-core processor has a clock speed of 2.8 GHz. Each core can execute one instruction per clock cycle. Calculate the maximum number of instructions the processor can execute per second. Give your answer in billions of instructions per second.
Medium
62.Describe the role of the control unit during the fetch stage of the fetch-decode-execute cycle.
Medium
63.Describe the role of the Memory Data Register (MDR) during the fetch stage of the fetch-decode-execute cycle.
Medium
64.A single-core processor has a clock speed of 3.2 GHz. Assuming it executes one instruction per clock cycle, calculate the number of instructions it can execute in 1 second. Give your answer in billions.
Easy
- A5.2 billion
- B4.2 billion
- C2.2 billion
- D3.2 billion
65.A quad-core processor has a clock speed of 2.5 GHz. Assuming each core can execute one instruction per clock cycle, what is the maximum number of instructions the processor can execute per second? Give your answer in billions of instructions per second.
Medium
- A12 billion instructions per second
- B10 billion instructions per second
- C9 billion instructions per second
- D11 billion instructions per second
66.A dual-core processor has a clock speed of 2.5 GHz. Assuming each core can execute one instruction per clock cycle, calculate the maximum number of instructions the processor can execute per second. Give your answer in billions of instructions per second.
Medium
- A4 billion instructions per second
- B6 billion instructions per second
- C7 billion instructions per second
- D5 billion instructions per second
67.A computer has a quad-core processor with a clock speed of 2.8 GHz. Assuming each core can execute one instruction per clock cycle, calculate the maximum number of instructions the computer can execute per second. Give your answer in billions.
Medium
- A12.2 billion instructions per second
- B13.2 billion instructions per second
- C11.2 billion instructions per second
- D10.2 billion instructions per second
68.A single-core processor has a clock speed of 3.2 GHz. If it can execute 2 instructions per clock cycle, how many instructions can it execute per second? Give your answer in billions.
Medium
- A5.4 billion instructions per second
- B8.4 billion instructions per second
- C6.4 billion instructions per second
- D7.4 billion instructions per second
69.A quad-core processor has a clock speed of 2.8 GHz. Each core can execute one instruction per clock cycle. Calculate the maximum number of instructions the processor can execute per second. Give your answer in billions of instructions per second.
Medium
- A13.2 billion instructions per second
- B11.2 billion instructions per second
- C10.2 billion instructions per second
- D12.2 billion instructions per second

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