The CPU and the fetch–decode–execute cycle

9.Match each CPU register/component with its primary role in the fetch-decode-execute cycle.

10.Put the following steps of the fetch stage in the correct order.

11.Which of the following are true about the program counter (PC)? (Select all that apply)

12.The control unit (CU) is responsible for decoding the instruction held in the current instruction register (CIR).

13.Match each stage to what happens during it.

14.Which of the following are true about the fetch-decode-execute cycle? (Select all that apply)

15.Arrange the following steps in the correct order for a simple instruction cycle.

16.In a pipelined CPU, what happens when the fetch stage of instruction 2 starts before the execute stage of instruction 1 has finished?

17.A computer has a CPU with 4 cores, each running at 2.5 GHz. Which of the following statements are true? (Select all that apply)

18.In a computer with a single-core CPU, if the clock speed is doubled, the number of instructions executed per second will always double.

19.Match each stage of the fetch-decode-execute cycle to the main action that happens during that stage.

20.During the fetch stage, after the address in the PC is copied to the MAR, what happens next?

21.In the fetch stage, the instruction is loaded into the MDR and then copied into which register?

22.Which of the following statements about the MDR are true? (Select all that apply)

23.The current instruction register (CIR) holds the instruction that is about to be executed, and it is used during the decode stage.

24.What does the ALU do during the execute stage?

25.When an interrupt occurs, what does the CPU do?

26.Which of the following is the correct order of the three main stages in the fetch-decode-execute cycle?

27.The program counter (PC) holds the memory address of the next instruction to be executed.

28.What is the role of the memory address register (MAR) in the fetch stage?

29.Which of the following statements about the memory data register (MDR) are true? (Select all that apply)

30.The program counter (PC) is incremented after the instruction is copied to the current instruction register (CIR).

31.What is the role of the arithmetic logic unit (ALU) during the execute stage?

32.Arrange the following steps of the fetch stage in the correct order.

33.Match each CPU component to its primary role in the fetch-decode-execute cycle.

34.Which of the following statements about the fetch-decode-execute cycle are true? (Select all that apply)

35.The memory data register (MDR) is used only for reading data from memory, not for writing data to memory.

36.During which stage does the CPU fetch the next instruction from memory?

37.Put the following steps in the correct order for a simple instruction cycle (without interrupts).

38.Match each stage of the fetch-decode-execute cycle to its main action.

39.Which of the following statements about the ALU and its role in the execute stage are true? (Select all that apply)

40.A CPU uses a pipeline where the fetch, decode, and execute stages each take 2 ns. If three instructions are processed sequentially without pipelining, how long (in ns) does it take to complete all three?

41.What is the name of the register that holds the memory address of the next instruction to be executed?

42.What is the name of the register that temporarily holds instructions read from memory?

43.Fill in the blanks with the three stages of the instruction cycle in order.

44.What is the name of the register that temporarily holds the instruction for decoding?

45.Fill in the blank: The ______ is a register that temporarily holds data read from memory or data to be written to memory.

46.What is the purpose of the decode stage in the fetch-decode-execute cycle?

47.How many main stages are there in the fetch-decode-execute cycle?

48.Fill in the blanks: During the ______ stage, the PC is polled for the address of the next instruction, and the instruction is eventually stored in the ______.

49.Explain how an interrupt affects the fetch-decode-execute cycle.

50.Calculate the total time in nanoseconds for one complete fetch-decode-execute cycle if each stage takes 2 ns and the stages are processed sequentially.

51.A CPU has a clock speed of 3 GHz. How many fetch-decode-execute cycles can it complete in one second if it executes one instruction per clock cycle?

52.Complete the sentence about the program counter.

53.A computer with a single-core CPU is running a program that performs a series of calculations. The CPU has a clock speed of 3 GHz and the program consists of 9 billion instructions. If the CPU executes on average one instruction per clock cycle, how long will the program take to run? Show your working.

54.Explain the purpose of the decode stage in the fetch-decode-execute cycle.

55.How many main stages are there in the fetch-decode-execute cycle?

56.A CPU has a clock speed of 3 GHz. How many fetch-decode-execute cycles can it complete in one second if it executes one instruction per clock cycle?